MS Thesis Defense

Towards Implementation of a Pattern Recognition System based on
a Working Theory of the Learning Rule for Dendritic Integration

Shamit Patel

4:00pm Monday 23 April 2012, ITE 346, UMBC

My goal is to develop a working theory of the learning rule for dendritic integration, and to then implement a pattern recognition system based on that learning algorithm so that the algorithm can be evaluated for its generalization ability. In this regard, this thesis presents an implementation of Jeff Hawkins and Dileep George's Hierarchical Temporal Memory (HTM) pattern recognition system that's based on an existing theory of the learning rule for dendritic integration – spike-timing-dependent synaptic plasticity (STDP). The integration of this learning rule is the novel contribution of this thesis. I found that the STDP HTM system achieved much higher probabilistic classification accuracy and better generalization ability than the non-STDP HTM system. Probabilistic classification accuracy is a way of measuring classification accuracy in which a testing pattern is classified correctly if its label appears in the group of labels output by the top-level node of the HTM network.

Committee: Professors Tim Oates (Chair), Yun Peng and Tim Finin

Pay:

·         $9.50/hour, paid bi-weekly through the University of Maryland, Baltimore County

Length of Time:

·         Approximately 40 hours a week, mostly on weekends

·         Runs from mid May, to end of August

Schedule:

·         Friday-Sunday, 11am-11pm

·         4 hours of Job Development/Readiness Shadowing during the week (to be determined based on schedule and availability)

Location:

·         Baltimore’s beautiful Inner Harbor, between the Science Center and the Visitor Center, parallel to Light Street

·         For the weekly 4 hours of Job Development/Readiness Shadowing, the Intern will start at our Cherry Hill office, located on 971 Seagull Ave, 21225

Responsibilities:

·         Provide directions to employees at the stand to ensure smooth operations

·         Keep track of timesheets and hours worked of employees

·         Monitor inventory and cash register receipts to make sure they match up after shifts/cash register switches.

·         Ensure proper customer service and that all customers are satisfied

·         Maintain quality of fruitshakes, grilled cheese sandwiches, and all other menu items

·         Stocking supplies and cleaning as necessary, and ensuring the cleanliness of the stand is being taken care of by employees

A year-long internship in Production Management for the Olney Theatre Center is available for 2012-2013. Located in the Washington, DC theatre community, this internship is a great opportunity for anyone interested in arts administration, specifically union relations, budgets, and other aspects of producing. Duties include generating weekly payroll, assembling contract packets for guest artists, and tracking expenses for the production department. On-campus housing and a weekly stipend is provided.

The ideal candidate would be proficient in Microsoft Excel, Access, and Word, have knowledge of financial terms, have a great sense of humor, be able to roll with the punches, and have a passion for theatre. If you are a student graduating this spring who fits this description, please submit your resume, along with a cover letter and three references to:

Mackenzie Douglas

Olney Theatre Center

mdouglas@olneytheatre.org

Ph.D. Dissertation Defense

DiffServ Assured Forwarded and Robust
Header Compression: Performance Analysis

Houcheng Lee

12:30pm Monday, 23 April 2012, ITE 201b

Performance analysis of network architecture and protocols can be done by using modeling and simulation or using emulation techniques. Modeling and simulation can be used to obtain qualitative results about a network protocol through building models of protocols under drastic abstractions. One major concern of the modeling approach is the fidelity of the results from a model simulation.

This dissertation presents detailed performance analyses of two major Internet standards using emulation techniques. The standards investigated are Differentiated Services (DiffServ) architecture and Robust Compression (ROHC) standard.

The DiffServ architecture was proposed to support quality of services (QoS) implementation in TCP/IP networks. In the first part of dissertation, a new and scalable approach to performance analysis of DiffServ architecture, based on fluid flow modeling approximation to TCP/UDP based traffic flows, is used to emulate millions of competing TCP and UDP flows across networks of various sizes, complexities and link speeds. The emulation involved real-world network constraints, including traffic prioritizations, limited buffers in routers, link congestion, active queue management (AQM) and packet drop policies on congested links. The results provided first quantitative understanding of the interactions of traffic with different drop precedencies in AF1 class traffic in a congested network.

The Robust Header Compression (ROHC) is proposed to implement efficient IP header compression on bandwidth constrained links in TCP/IP networks. In the second part of dissertation, an emulation tool, called CORE, developed at NRL is used to analyze the performance of ROHC. ROHC compresses packet headers at a sender side, and decompresses them at the receiver side to increase efficiency of a communication link. The results provided quantitative understanding of compression gains from using ROHC standard for compressing IPv4/UDP and IPv6/UDP traffic on links.

Committee:

• Dr. Deepinder Sidhu
• Dr. Yelena Yesha
• Dr. Konstantinos Kalpakis
• Dr. Ted M. Foster
• Dr. Edward Zieglar

Congratulations to our Computer Science and Electrical Engineering undergraduate students who have recently been selected as Undergraduate Research Award (URA)Scholars. The URA provides undergraduates with up to $1,500 to fund their original research projects. The work is done in conjunction with a faculty mentor, and is then presented at UMBC's  Undergraduate Research and Creative Achievement Day (URCAD) in April. This year, these students and their faculty advisors will be recognized at URCAD on Wednesday, April 25 at noon in the University Center, Room 312.

David Eisen
Computer Engineering, Senior
Faculty Advisor: Fow-Sen Choa

David’s research focuses on the study of cultured neuron inhibition and excitation via optical stimuli from mid-IR (MIR) quantum cascade lasers (QCL).

“It was very exciting news to hear my URA proposal was accepted. This is my first research experience and proposal, so I believe this award will give me the confidence to pursue other opportunities in the future. The URA will give me a hands-on learning experience in the field of photonics research by working alongside Professor Choa as well as graduate students. Not only does this look good on a resume, but it gives me a chance to really get a taste for what real world challenges and rewards await after graduation.”

Julian Field
Computer Engineering, Junior
Faculty Advisor: Tinoosh Mohsenin

Julian will be doing research in UMBC's Energy Efficient and High Performance Computing Lab. His task will be the development and mapping of a many-core processor for the purpose of performing ultrasound imaging applications. Many cores on the processor will improve performance and reduce the running time of the processes. The processor will be designed using the Verilog hardware description language (HDL) and will be implemented by programming the design into a Field-Programmable Gate Array (FPGA). Using an FPGA not only reduces the cost of the design, but it also speeds up implementation.

"I felt very honored to receive the award, and I believe that it is going to help me in several ways. It allows me to get paid for doing research in a field that fascinates me and in which I hope to work in the future. Besides the obvious financial benefit, the award adds weight to my research when I list it on my resume, and this should be of great value when I apply to graduate school and for Computer Engineering jobs and internships in the future."

Thomas A Hervey
Information Systems/ Geography, Sophomore
Aneep Bindra
Computer Science, Sophomore
Zachary Hullihen
Computer Science, Junior
Faculty Advisor: Marc Olano 

"Lights, Camera, Motion, Action: The Dance Application of Microsoft's Kinect and Intelligent Stage Lighting."

"Receiving this award has given me a stronger incentive to work my hardest and apply myself beyond [the] academic realm. This award will be beneficial because it will provide necessary funds for unusual but necessary research tools. I look forward to strengthening my presentation skills at URCAD next year as well as refining my organizational skills through planned documentation and procedures during the actual experimentation. The award overall certainly creates a sense of confidence within the research community. I find it likely that students that are not active in research will hear about the award and benefits through their friends' experiences, and current URA scholars will continue research through new projects." -Thomas A. Hervey

Alex Morrow
Computer Science, Sophomore
Faculty Advisor: Marie desJardins

"Quantitative Evaluation of Dimension Reduction for Visualization and Analysis."

Alex’s research branches off of his current research on visualization and analysis techniques to facilitate user understanding of the uncertainty associated with statistical models that have been learned from data. Alex will analyze and evaluate dimension reduction methods. Using a set of quantitative metrics compiled by his research advisors Dr. Marie desJardins and Dr. Penny Rheingans, Alex will compare the performance of several dimension reduction techniques in a number of different application domains.

Adam Page
Computer Engineering / Math
Faculty Advisor: Dr. Tinoosh Mohsenin

Adam’s research involves designing an energy efficient and high performance error correction Low Density Parity Check Decoder circuit for IEEE 802.11ad standard, the next generation of Wireless Local Arena Network (WLAN). The design will include an efficient architecture for the decoder using Verilog coding and VLSI implementation.

“I am both honored and excited to receive this award. I know the URA will give me the opportunity to apply knowledge I have gained from all of my courses into a real world application.”

Don’t forget to meet our URA scholars at URCAD next Wednesday, April 25 at noon in the University Center, Room 312.